- BS in Electrical Engineering or comparable engineering discipline- 9+ years of digital verification engineering experience using industry standard simulation tools (7+ years with an MS, 4 years with a PhD)- Advanced Knowledge of UVM and use of a coverage-driven verification methodology.
- Experience developing testplans, leading testplan reviews, test development and RTL debug.
- Active Secret Clearance or higher.
- MS in Electrical Engineering or comparable engineering discipline.
- Experience with data structures, object oriented programming languages and concepts- Experience with Verification IP integration and/or development.
- Experience with a coverage-driven verification methodology from planning through closure.
- Knowledge of industry standard bus or I/O interfaces- Experience with SystemVerilog Assertions (SVA).
- FPGA/ASIC design and/or development process experience.
- Experience with scripting languages (Bash, Perl, Python, Tcl, Makefile)- Knowledge of digital signal processing.
- Active Top Secret Clearance or higher.
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